1. Field of the Invention
The present invention relates to a display controller for controlling a display apparatus used as a display apparatus for an electronic apparatus such as a personal computer and having a memory function such as a ferroelectric liquid crystal display apparatus or a liquid crystal display apparatus with a display data storage function, and more particularly to a technique for reduction of power consumption of an entire display system including a display apparatus and a display controller of the type mentioned.
2. Description of the Related Art
Conventionally, display apparatus having a memory function such as a ferroelectric liquid crystal display apparatus disclosed in Japanese Patent Laid-Open No. Hei 63-063094 and a liquid crystal display apparatus with a display data storage circuit disclosed in Japanese Patent Laid-Open No. Hei 9-258168 are known as display apparatus of low power consumption for use with an electronic apparatus such as a personal computer. Where a display apparatus having a memory function is used, a variation in display data must be detected in order to make the most of the characteristic of the display apparatus of the type that data thereon should be rewritten only for those pixels with which data to be displayed are varied. Conventionally, for the detection of such variation of data (such detection is hereinafter referred to as rewriting detection), generally two methods described below are used.
In a first one of the methods, display data outputted from a display controller having no writing detection function are passed through a display conversion apparatus having a writing detection function to drive a display apparatus having a memory function. The method is disclosed in Japanese Patent Laid-Open No. Hei 10-11034.
FIG. 19 shows an apparatus which employs the first method. Referring to FIG. 19, a display conversion apparatus 81 connected to a display controller 79 which has no rewriting detection function includes a frame buffer 82 for temporarily storing display data for one screen (one frame), and a difference detection and display control circuit 83 for detecting a finite difference between two sets of display data and signaling only necessary display data at a timing requested by a display apparatus 3 having a memory function to the display apparatus 3. The display controller 79 outputs display data for the current screen as a display data signal 84, and the frame buffer 82 stores the display data. Simultaneously, the frame buffer 82 outputs display,data for the last screen as another display data signal 85. The difference detection and display control circuit 83 compares the display data signal 84 and the display data signal 86 with each other and outputs, when the display data signal 84 and the display data signal 85 are different from each other, a display data signal 86 to the display apparatus 3.
FIG. 20 shows the display controller 79 and elements associated with the display controller 79. Referring to FIG. 20, the display controller 79 includes a graphic engine 6 for producing display data based on a plotting instruction and plotting data 11 from a host CPU 1 and writing the display data into a video memory (hereinafter referred to simply as VRAM) 4, a refresh control circuit 10 for reading out the display data from the VRAM 4 in a fixed period and signaling the display data to a display apparatus 80, and a VRAM arbitration circuit 8 for arbitrating a VRAM access right between the graphic engine 6 and the refresh control circuit 10. It is to be noted that reference numeral 14 denotes an internal VRAM enabling signal, 15 a VRAM control signal set, 16 a VRAM data signal set, 19 a VRAM request signal, 23 a display control signal set, 24 an updating signal, 25 a memory clock signal, and 26 a display clock signal.
The second method corresponds to an arrangement wherein the display controller 79 shown in FIG. 20 has an internal function for detecting write accessing of the graphic engine 6 to the VRAM 4 (refer to Japanese Patent Laid-Open No. Hei 8-248391).
FIG. 21 shows an apparatus which employs the second method. Referring to FIG. 21, if a writing detection circuit 88 in a display controller 87 for a display apparatus having a memory function detects write accessing of a graphic engine 6 to a VRAM 4 through supervision of a VRAM bus 91, then it discriminates from a write address of the write accessing to which scanning line on the display apparatus 3 the write accessing is directed. Then, the writing detection circuit 88 sends an updating flag signal 90 to the display control circuit 89 to deliver the number of the scanning line and information that rewriting of display data has occurred. Based on the information, the display control circuit 89 signals a display data signal 92 representative of display data only for the scanning line, for which the display data has been rewritten, to the display apparatus 3.
The conventional rewriting detection methods described above, however, have the following problems.
With the first method, a frame buffer having an equal memory capacity to that of a VRAM must be provided separately from the VRAM. This increases the number of parts and the cost Further, in order to allow display data to be displayed, both of the VRAM and the frame buffer must be accessed, which gives rise to a problem of an increase of power consumption.
With the second method, since rewriting detection is detection of mere write accessing and no attention is paid to a variation of data, also an operation to xe2x80x9cwrite data same as currently stored dataxe2x80x9d is discriminated as xe2x80x9crewrittenxe2x80x9d and rewriting also for pixels which need not be updated occurs. This results in failure in sufficiently exhibiting the advantage of a display apparatus having a memory function. In other words, the second method has a problem in that power consumption cannot be reduced efficiently.
It is an object of the present invention to provide a display controller for a display apparatus having a memory function which can reduce power consumption efficiently.
In order to attain the object described above, according to the present invention, there is provided a display controller for controlling a display apparatus having a memory function, comprising display updating apparatus for updating a display of the display apparatus, display data storage means, display data production means for producing and writing display data into the display data storage means, rewriting comparison means for detecting by comparison whether or not rewriting of data in a line, which is a set of pixels including a certain number of successive pixels on one scanning line of the display apparatus and is used as a unit of comparison, into the display data storage means has occurred, rewriting information storage means for storing comparison information of a result of the comparison of the rewriting comparison means into a corresponding address thereof, and rewriting control means for checking, prior to updating of the display by the display updating means, the address of the writing information storage means and, only when stored contents of the address represent rewriting of different data, reading the data from the display data storage means and signaling the data to the display apparatus through the display updating means.
Since the display apparatus having a display function has a characteristic that it requires updating of a display only for pixels whose display data vary, updating of the display of the display apparatus is performed periodically (for example, several tens times/second or more) by the display updating means. On the other hand, it is detected by the rewriting comparison means whether or not rewriting of different data by the display data production means for a line of those pixels with regard to which updating of the display is to be performed currently has occurred since the last display updating, and resulting information is stored into the rewriting information storage means. The rewriting control means checks the address of the display data storage means prior to the updating of the display and, only when the data at the address of the display data storage means has been rewritten since the last display updating, the rewriting control means performs reading in of the data from the display data storage means and signaling of the data to the display apparatus having a memory function.
The display data storage means may include the rewriting comparison means for detecting by comparison whether or not rewriting of data has occurred. In this instance, the rewriting comparison means may latch and compare potentials to detect whether or not rewriting of data has occurred.
The display controller may further comprise arbitration means for arbitrating accessing of the display data production means to the display data storage means and accessing of the rewriting comparison means to the rewriting information storage means.
The display controller may further comprise line size variation means for varying the number of pixels which form a line as the unit of rewriting comparison.
The display controller for a display apparatus having a memory construction is advantageous in that the power consumption of the display apparatus having a memory function and the display data storage means can be reduced. This is because accessing to the display apparatus and the display data storage means which occurs in order to display an image is required only for each line which includes pixels with regard to which display data have varied. On the other hand, accessing to the rewriting information storage means is required. However, the accessing frequency (which varies depending upon the size of the line) is reduced to one nth when compared with the accessing frequency to display data storage means in a conventional memory controller where n is the size of the line, and the comparison information requires only the smallest data width of one bit. Therefore, the increase of accessing caused by the accessing to the rewriting information storage means is much smaller than the decrease of accessing described above.
Where the display controller includes the line size variation means, the power consumption can be reduced more efficiently by increasing the line size when rewriting of the display occurs less frequency and decreasing the line size when rewriting of the display occurs comparatively frequently.
The display controller for a display apparatus having a memory function is advantageous also in augmentation of the performance of the display system. This is because the decrease of accessing to the display data storage means signifies an increase of the period within which the display data production means possesses an access right to the display data storage means and consequently the waiting time for accessing of the display data production means to the display data storage means decreases when compared with that in a conventional display controller.